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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
5.20.1
General-Purpose Input/Output Peripheral Register Descriptions
The external parallel port interface includes a 16-bit general purpose I/O that can be individually
programmed as input or output with interrupt capability. Control of the general purpose I/O is maintained
through a set of I/O memory-mapped registers shown in Table 5-54 .
Table 5-54. GPIO Registers
HEX ADDRESS
RANGE
1C06h
1C07h
1C08h
1C09h
1C0Ah
1C0Bh
1C0Ch
1C0Dh
1C0Eh
1C0Fh
1C10h
1C11h
ACRONYM
IODIR1
IODIR2
IOINDATA1
IOINDATA2
IODATAOUT1
IODATAOUT2
IOINTEDG1
IOINTEDG2
IOINTEN1
IOINTEN2
IOINTFLG1
IOINTFLG2
REGISTER NAME
GPIO Direction Register 1
GPIO Direction Register 2
GPIO Data In Register 1
GPIO Data In Register 2
GPIO Data Out Register 1
GPIO Data Out Register 2
GPIO Interrupt Edge Trigger Enable Register 1
GPIO Interrupt Edge Trigger Enable Register 2
GPIO Interrupt Enable Register 1
GPIO Interrupt Enable Register 2
GPIO Interrupt Flag Register 1
GPIO Interrupt Flag Register 2
148
Peripheral Information and Electrical Specifications
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